"Chervill"
- 期刊名称Notes and Queries
- 作者W. H. J.,
- 卷第182卷
- 期第8期
- 印刷ISSN0029-3970
- 电子ISSN1471-6941
- 文件大小205.09KB
- 发表时间1942-02-21
- DOI10.1093/nq/182.8.109
- 页码109-110
8-Bit Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic UnitFilippov, T.; Dorojevets, M.; Sahu, A.; Kirichenko, A.; Ayala, C.; Mukhanov, O. · IEEE Transactions on Applied Superconductivity · 2011
Logic Design of a 16-bit Bit-Slice Arithmetic Logic Unit for 32-/64-bit RSFQ MicroprocessorsTang, Guang-Ming; Qu, Pei-Yao; Ye, Xiao-Chun; Fan, Dong-Rui · IEEE Transactions on Applied Superconductivity · 2018
4-bit Bit-Slice Arithmetic Logic Unit for 32-bit RSFQ MicroprocessorsTang, Guang-Ming; Takata, Kensuke; Tanaka, Masamitsu; Fujimaki, Akira; Takagi, Kazuyoshi; Takagi, Naofumi · IEEE Transactions on Applied Superconductivity · 2015
20 GHz Operation of an Asynchronous Wave-Pipelined RSFQ Arithmetic-Logic UnitTimur V. Filippov; Anubhav Sahu; Alex F. Kirichenko; Igor V. Vernik; Mikhail Dorojevets; Christopher L. Ayala; Oleg A. Mukhanov · 2012
8-Bit Asynchronous Sparse-Tree Superconductor RSFQ Arithmetic-Logic Unit With a Rich Set of OperationsDorojevets, M.; Ayala, C. L.; Yoshikawa, N.; Fujimaki, A. · IEEE Transactions on Applied Superconductivity · 2013
[IEEE 2019 IEEE International Superconductive Electronics Conference (ISEC) - Riverside, CA, USA (2019.7.28-2019.8.1)] 2019 IEEE International Superconductive Electronics Conference (ISEC) - qBSA: Logic Design of a 32-bit Block-Skewed RSFQ Arithmetic Logic UnitKundu, Souvik; Datta, Gourav; Beerel, Peter A.; Pedram, Massoud · 2019
[IEEE 2015 15th International Superconductive Electronics Conference (ISEC) - Nagoya, Japan (2015.7.6-2015.7.9)] 2015 15th International Superconductive Electronics Conference (ISEC) - 80-GHz Operation of an 8-Bit RSFQ Arithmetic Logic UnitAndo, Yuki; Sato, Ryo; Tanaka, Masamitsu; Takagi, Kazuyoshi; Takagi, Naofumi · 2015