Josephson 4 K-bit cache memory design for a prototype signal processor. I. General overview

• 作者W. H. Henkels; L. M. Geppert; J. Kadlec; P. W. Epperlein; H. Beha; W. H. Chang; H. Jaeckel
• 文件大小1021.75KB
• 发表时间1985
• DOI10.1063/1.335960