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A 32 b LISP processor: K Watanabe, A Ishikawa, Y Yamada, Y Hibino (Electr. Commun. Labs., NTT, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.200–201, 401

A 32 b LISP processor: K Watanabe, A Ishikawa, Y Yamada, Y Hibino (Electr. Commun. Labs., NTT, Tokyo, Japan) 1987 IEEE International Solid State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition, New York, USA, 25–27 Feb. 1987 (Coral Gables, FL, USA: Lewis Winner, Feb. 1987), pp.200–201, 401

卷第19卷
期第5期
印刷ISSN0026-2692
文件大小97.89KB
发表时间1988
DOI10.1016/s0026-2692(88)80166-6

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