A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC
- 作者Nogami, K.; Sakurai, T.; Sawada, K.; Sakaue, K.; Miyazawa, Y.; Tanaka, S.; Hiruta, Y.; Katoh, K.; Takayanagi, T.; Shirotori, T.; Itoh, Y.; Uchida, M.; Iizuka, T.
- 卷第25卷
- 期第1期
- 文件大小845.32KB
- 发表时间1990
- DOI10.1109/4.50291
- 页码100-108
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[Japan Soc. Applied Phys 1995 Symposium on VLSI Circuits. Digest of Technical Papers - Kyoto, Japan (8-10 June 1995)] Digest of Technical Papers., Symposium on VLSI Circuits. - A current direction sense technique for multi-port SRAMsIzumikawa, M.; Yamashina, M. · 1995
[IEEE IEEE 1995 Custom Integrated Circuits Conference - Santa Clara, CA, USA (1-4 May 1995)] Proceedings of the IEEE 1995 Custom Integrated Circuits Conference - 100 MHz, 0.55 mm/sup 2/, 2 mW, 16-b stacked-CMOS multiplier-accumulatorIgura, H.; Izumikawa, M.; Furuta, K.; Ito, H.; Wakabayashi, H.; Nakajima, K.; Mogami, T.; Horiuchi, T.; Yamashina, M. · 1995
[IEEE ISSCC '95 - International Solid-State Circuits Conference - San Francisco, CA, USA (15-17 Feb. 1995)] Proceedings ISSCC '95 - International Solid-State Circuits Conference - A 0.9 V 100 MHz 4 mW 2 mm/sup 2/ 16 b DSP coreIzumikawa, M.; Igura, H.; Furuta, K.; Ito, H.; Wakabayashi, H.; Nakajima, K.; Mogami, T.; Horiuchi, T.; Yamashina, M. · 1995