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[IEEE Proceedings of IEEE International Electron Devices Meeting - San Francisco, CA, USA (1989.12.3-1989.12.6)] International Technical Digest on Electron Devices Meeting - 3-D topography simulation of via holes using generalized solid modeling

[IEEE Proceedings of IEEE International Electron Devices Meeting - San Francisco, CA, USA (1989.12.3-1989.12.6)] International Technical Digest on Electron Devices Meeting - 3-D topography simulation of via holes using generalized solid modeling

Tazawa, ; Leon, ; Anderson, ; Abe, ; Saito, ; Yoshii, ; Scharfetter,
  • 作者Tazawa, ; Leon, ; Anderson, ; Abe, ; Saito, ; Yoshii, ; Scharfetter,
  • 文件大小359.10KB
  • 发表时间1992
  • DOI10.1109/iedm.1992.307335
  • 页码173-176
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