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[IEEE Symposium on VLSI Technology - Kyoto, Japan (1997.06.12-1997.06.12)] Symposium on VLSI Technology - Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/)

[IEEE Symposium on VLSI Technology - Kyoto, Japan (1997.06.12-1997.06.12)] Symposium on VLSI Technology - Modeling And Characterization Of N/sup +/- And P/sup +/-polysilicon-gated Ultra Thin Oxides (21-26 /spl Aring/)

Lo, ; Buchanan, ; Taur, ; Han, ; Wu,

作者Lo, ; Buchanan, ; Taur, ; Han, ; Wu,
文件大小231.61KB
发表时间1997
DOI10.1109/VLSIT.1997.623742
页码149-150

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