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[IEEE Comput. Soc 32nd IEEE International Symposium on Multi-Valued Logic - Boston, MA, USA (15-18 May 2002)] Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic - Multi-valued flip-flop with neuron-CMOS NMIN circuits

[IEEE Comput. Soc 32nd IEEE International Symposium on Multi-Valued Logic - Boston, MA, USA (15-18 May 2002)] Proceedings 32nd IEEE International Symposium on Multiple- Valued Logic - Multi-valued flip-flop with neuron-CMOS NMIN circuits

Inaba, M.; Tanno, K.; Ishizuka, O.

作者Inaba, M.; Tanno, K.; Ishizuka, O.
文件大小984.87KB
发表时间2002
DOI10.1109/ismvl.2002.1011100
页码282-288

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