[IEEE IEEE International Electron Devices Meeting 2003 - Washington, DC, USA (8-10 Dec. 2003)] IEEE International Electron Devices Meeting 2003 - Process-strained Si (PSS) CMOS technology featuring 3D strain engineering
Ge, C.-H.; Lin, C.-C.; Ko, C.-H.; Huang, C.-C.; Huang, Y.-C.; Chan, B.-W.; Perng, B.-C.; Sheu, C.-C.; Tsai, P.-Y.; Yao, L.-G.; Wu, C.-L.; Lee, T.-L.; Chen, C.-J.; Wang, C.-T.; Lin, S.-C.; Yeo, Y.-C.; Hu, C.
- 作者Ge, C.-H.; Lin, C.-C.; Ko, C.-H.; Huang, C.-C.; Huang, Y.-C.; Chan, B.-W.; Perng, B.-C.; Sheu, C.-C.; Tsai, P.-Y.; Yao, L.-G.; Wu, C.-L.; Lee, T.-L.; Chen, C.-J.; Wang, C.-T.; Lin, S.-C.; Yeo, Y.-C.; Hu, C.
- 文件大小272.63KB
- 发表时间2003
- DOI10.1109/iedm.2003.1269169