[IEEE International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) - Bialystok, Poland (13-17 Sept. 2006)] International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06) - Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels
- 作者Siegel, S.; Schaffer, R.; Merker, R.
- 文件大小279.46KB
- 发表时间2006
- DOI10.1109/parelec.2006.33
- 页码173-180
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