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[IEEE Design Languages (FDL) - Stuttgart (2008.09.23-2008.09.25)] 2008 Forum on Specification, Verification and Design Languages - VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

[IEEE Design Languages (FDL) - Stuttgart (2008.09.23-2008.09.25)] 2008 Forum on Specification, Verification and Design Languages - VEST - An intelligent tool for timing SoCs verification using UML timing diagrams

Pulka, Andrzej; Milik, Adam

作者Pulka, Andrzej; Milik, Adam
文件大小997.33KB
发表时间2008
DOI10.1109/fdl.2008.4641432
页码118-123

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