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[IEEE 2009 10th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2009.03.16-2009.03.18)] 2009 10th International Symposium on Quality of Electronic Design - A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations

[IEEE 2009 10th International Symposium on Quality of Electronic Design (ISQED) - San Jose, CA, USA (2009.03.16-2009.03.18)] 2009 10th International Symposium on Quality of Electronic Design - A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations

Bhattacharya, Koustav; Ranganathan, Nagarajan

作者Bhattacharya, Koustav; Ranganathan, Nagarajan
文件大小4722.56KB
发表时间2009
DOI10.1109/isqed.2009.4810326
页码388-393

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