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[IEEE 2011 International Symposium on Low Power Electronics and Design (ISLPED) - Fukuoka, Japan (2011.08.1-2011.08.3)] IEEE/ACM International Symposium on Low Power Electronics and Design - 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<inf>DD</inf>) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated V<inf>DD</inf> between flip-flops and combinational logics

[IEEE 2011 International Symposium on Low Power Electronics and Design (ISLPED) - Fukuoka, Japan (2011.08.1-2011.08.3)] IEEE/ACM International Symposium on Low Power Electronics and Design - 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2V to 310mV enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics

Fuketa, Hiroshi; Hirairi, Koji; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu
  • 作者Fuketa, Hiroshi; Hirairi, Koji; Yasufuku, Tadashi; Takamiya, Makoto; Nomura, Masahiro; Shinohara, Hirofumi; Sakurai, Takayasu
  • 文件大小851.39KB
  • 发表时间2011
  • DOI10.1109/islped.2011.5993630
  • 页码163-168
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