[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - Saving 78.11% Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU
- 作者Minh Thien Trieu, ; Huong Thien Hoang, ; Phong The Vo, ; Hung Bao Vo, ; Yuyama, Yoichi
- 文件大小794.05KB
- 发表时间2011
- DOI10.1109/ASICON.2011.6157117
- 页码39-42
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