[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs
Wang, Jinn-Shyan; Yung-Chen Chien, ; Jia-Hong Lin, ; Cheng, Chun-Yuan; Ying-Ting Ma, ; Chung-Hsun Huang,
- 作者Wang, Jinn-Shyan; Yung-Chen Chien, ; Jia-Hong Lin, ; Cheng, Chun-Yuan; Ying-Ting Ma, ; Chung-Hsun Huang,
- 文件大小1200.57KB
- 发表时间2011
- DOI10.1109/asicon.2011.6157119
- 页码47-50