Dynamic Thermal Clock Skew Compensation Using Tunable Delay BuffersChakraborty, Ashutosh; Duraisami, Karthik; Sathanur, Ashoka; Sithambaram, Prassanna; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2008

[ACM Press the 2007 international symposium - Portland, OR, USA (2007.08.27-2007.08.29)] Proceedings of the 2007 international symposium on Low power electronics and design - ISLPED '07 - Timing-driven row-based power gatingSathanur, Ashoka; Pullini, Antonio; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo · 2007

[ACM Press the 18th ACM Great Lakes symposium - Orlando, Florida, USA (2008.05.04-2008.05.06)] Proceedings of the 18th ACM Great Lakes symposium on VLSI - GLSVLSI '08 - Optimal sleep transistor synthesis under timing and area constraintsSathanur, Ashoka; Pullini, Antonio; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo · 2008

[ACM Press Proceeding of the thirteenth international symposium - Bangalore, India (2008.08.11-2008.08.13)] Proceeding of the thirteenth international symposium on Low power electronics and design - ISLPED '08 - Multiple power-gating domain (multi-VGND) architecture for improved leakage power reductionSathanur, Ashoka; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo · 2008

[ACM Press the 17th great lakes symposium - Stresa-Lago Maggiore, Italy (2007.03.11-2007.03.13)] Proceedings of the 17th great lakes symposium on Great lakes symposium on VLSI - GLSVLSI '07 - Design of a family of sleep transistor cells for a clustered power-gating flow in 65nm technologyCalimera, Andrea; Pullini, Antonio; Sathanur, Ashoka Visweswara; Benini, Luca; Macii, Alberto; Macii, Enrico; Poncino, Massimo · 2007

mwJFS: A Multiwrite-Mode Journaling File System for MLC NVRAM StoragesChen, Shuo-Han; Chang, Yuan-Hao; Chang, Yu-Ming; Shih, Wei-Kuan · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2019