[IEEE 2012 International Symposium on Electronic System Design (ISED) - Kolkata, India (2012.12.19-2012.12.22)] 2012 International Symposium on Electronic System Design (ISED) - Design and Analysis of a Robust, High Speed, Energy Efficient 18 Transistor 1-bit Full Adder Cell, Modified with the Concept of MVT Scheme
- 作者Basak, Subhramita; Saha, Dipankar; Mukherjee, Sagar; Chatterjee, Sayan; Sarkar, C.K.
- 文件大小202.36KB
- 发表时间2012
- DOI10.1109/ised.2012.23
- 页码130-134
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