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[IEEE 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Paris, France (2014.7.8-2014.7.10)] 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing

[IEEE 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - Paris, France (2014.7.8-2014.7.10)] 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH) - STT-MRAM based low power synchronous non-volatile logic with timing demultiplexing

Huang, Kejie; Zhao, Rong; Lian, Yong

作者Huang, Kejie; Zhao, Rong; Lian, Yong
文件大小259.02KB
发表时间2014
DOI10.1109/nanoarch.2014.6880495
页码31-36

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