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[IEEE 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL) - Bremen, Germany (2014.5.19-2014.5.21)] 2014 IEEE 44th International Symposium on Multiple-Valued Logic - Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme

[IEEE 2014 IEEE 44th International Symposium on Multiple-Valued Logic (ISMVL) - Bremen, Germany (2014.5.19-2014.5.21)] 2014 IEEE 44th International Symposium on Multiple-Valued Logic - Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme

Harada, Shintaro; Bai, Xu; Kameyama, Michitaka; Fujioka, Yoshichika
  • 作者Harada, Shintaro; Bai, Xu; Kameyama, Michitaka; Fujioka, Yoshichika
  • 文件大小1830.68KB
  • 发表时间2014
  • DOI10.1109/ismvl.2014.45
  • 页码214-219
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