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A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR <formula><tex>(textbf {>}textbf{50})</tex></formula> dB Up to 1 GHz

A 28-nm CMOS 7-GS/s 6-bit DAC With DfT Clock and Memory Reaching SFDR (textbf {>}textbf{50}) dB Up to 1 GHz

Radulov, Georgi I.; Quinn, Patrick J.; van Roermund, Arthur H. M.

期刊名称IEEE Transactions on Very Large Scale Integration (VLSI) Systems
作者Radulov, Georgi I.; Quinn, Patrick J.; van Roermund, Arthur H. M.
印刷ISSN1063-8210
电子ISSN1557-9999
文件大小1412.98KB
发表时间2014
DOI10.1109/TVLSI.2014.2350540
页码1-1

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