[IEEE 2014 IEEE Symposium on VLSI Technology - Honolulu, HI, USA (2014.6.9-2014.6.12)] 2014 Symposium on VLSI Technology (VLSI-Technology): Digest of Technical Papers - Ultra thinning down to 4-µm using 300-mm wafer proven by 40-nm node 2Gb DRAM for 3D multi-stack WOW applications
Kim, Y. S.; Kodama, S.; Mizushima, Y.; Maeda, N.; Kitada, H.; Fujimoto, K.; Nakamura, T.; Suzuki, D.; Kawai, A.; Arai, K.; Ohba, T.
- 作者Kim, Y. S.; Kodama, S.; Mizushima, Y.; Maeda, N.; Kitada, H.; Fujimoto, K.; Nakamura, T.; Suzuki, D.; Kawai, A.; Arai, K.; Ohba, T.
- 文件大小997.40KB
- 发表时间2014
- DOI10.1109/vlsit.2014.6894347
- 页码1-2