A 1.1 V 10-bit 62MS/s pipeline ADC with two-step non-overlapping clock generation for multi I-Q channel RF receivers
- 期刊名称Analog Integrated Circuits and Signal Processing
- 作者Ju, Hyungyu; Lee, Minjae
- 印刷ISSN0925-1030
- 电子ISSN1573-1979
- 文件大小2899.46KB
- 发表时间2016-4-5
- DOI10.1007/s10470-016-0734-0
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