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Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time $$Delta Sigma$$ Δ Σ modulator with 15 MHz bandwidth and 60 dB dynamic range

Design-to-testing: a low-power, 1.25 GHz, single-bit single-loop continuous-time $$Delta Sigma$$ Δ Σ modulator with 15 MHz bandwidth and 60 dB dynamic range

Balagopal, Sakkarapani; Zhu, Kehan; Wu, Xinyu; Saxena, Vishal

期刊名称Analog Integrated Circuits and Signal Processing
作者Balagopal, Sakkarapani; Zhu, Kehan; Wu, Xinyu; Saxena, Vishal
印刷ISSN0925-1030
电子ISSN1573-1979
文件大小1969.82KB
发表时间2016-9-16
DOI10.1007/s10470-016-0865-3

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