[IEEE 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) - Porto Alegre, Brazil (2016.5.8-2016.5.11)] 2016 22nd IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC) - Analysis and Design of Delay Lines for Dynamic Voltage Scaling Applications
Tadros, Ramy N.; Hua, Weizhe; Gibiluka, Matheus; Moreira, Matheus T.; Calazans, Ney L. V.; Beerel, Peter A.
- 作者Tadros, Ramy N.; Hua, Weizhe; Gibiluka, Matheus; Moreira, Matheus T.; Calazans, Ney L. V.; Beerel, Peter A.
- 文件大小293.48KB
- 发表时间2016
- DOI10.1109/ASYNC.2016.16
- 页码11-18