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[IEEE 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) - Taipei, Taiwan (2016.10.15-2016.10.19)] 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) - C
              <sup>3</sup>
              D: Mitigating the NUMA bottleneck via coherent DRAM caches

[IEEE 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) - Taipei, Taiwan (2016.10.15-2016.10.19)] 2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO) - C 3 D: Mitigating the NUMA bottleneck via coherent DRAM caches

Huang, Cheng-Chieh; Kumar, Rakesh; Elver, Marco; Grot, Boris; Nagarajan, Vijay
  • 作者Huang, Cheng-Chieh; Kumar, Rakesh; Elver, Marco; Grot, Boris; Nagarajan, Vijay
  • 文件大小468.51KB
  • 发表时间2016
  • DOI10.1109/MICRO.2016.7783739
  • 页码1-12
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