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[IEEE 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) - Haining (2017.12.14-2017.12.16)] 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) - On-chip layout optimization of synchronous DC-DC buck converter for EMI reduction

[IEEE 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) - Haining (2017.12.14-2017.12.16)] 2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS) - On-chip layout optimization of synchronous DC-DC buck converter for EMI reduction

Joo, Soyeon; Hwang, Jisoo; Song, Eunseok; Kim, SoYoung

作者Joo, Soyeon; Hwang, Jisoo; Song, Eunseok; Kim, SoYoung
文件大小466.54KB
发表时间2017
DOI10.1109/EDAPS.2017.8277036
页码1-3

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