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[IEEE 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Chicago, IL (2018.10.8-2018.10.10)] 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - A Method to Model Statistical Path Delays for Accurate Defect Coverage

[IEEE 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - Chicago, IL (2018.10.8-2018.10.10)] 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) - A Method to Model Statistical Path Delays for Accurate Defect Coverage

Javvaji, Pavan Kumar; Tragoudas, Spyros
  • 作者Javvaji, Pavan Kumar; Tragoudas, Spyros
  • 文件大小800.63KB
  • 发表时间2018
  • DOI10.1109/DFT.2018.8602962
  • 页码1-6
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