海量图书期刊资源,随时随地畅享阅读乐趣
[IEEE 9th International Symposium on Quality Electronic Design (isqed 2008) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - Table of Contents2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - Luncheon Keynote SpeechDomic, Antun · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - System Verilog for Quality of Results (QoR)Surepeddi, Ravi · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - Strategies for Quality CAD PDKsGadepally, Kamesh V.; Young, Mark; Lin, James; Franklin, Andy; Perumal, Ravi; Joshi, Sridhar · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - Processor Verification with hwBugHuntSudhakrishnan, Sangeetha; Su, Liying; Renau, Jose · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - High-Quality Circuit Synthesis for Modern TechnologiesJozwiak, Lech; Chojnacki, Artur; Slusarczyk, Aleksander · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - A Basis for Formal Robustness CheckingFey, Goerschwin; Drechsler, Rolf · 2008
[IEEE 2008 9th International Symposium of Quality of Electronic Design (ISQED) - San Jose, CA, USA (2008.03.17-2008.03.19)] 9th International Symposium on Quality Electronic Design (isqed 2008) - Runtime Validation of Transactional Memory SystemsChen, Kaiyu; Malik, Sharad; Patra, Priyadarsan · 2008
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test TimePrashant Dubey; Akhil Garg; Shashank Mahajan · 2010
[IEEE 2006 IEEE International SOC Conference - Austin, TX (2006.09.24-2006.09.27)] 2006 IEEE International SOC Conference - Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip CostGarg, Akhil; Dubey, Prashant · 2006
[IEEE 2007 IEEE International Symposium on Circuits and Systems - New Orleans, LA, USA (2007.05.27-2007.05.30)] 2007 IEEE International Symposium on Circuits and Systems - GALS Based Shared Test Architecture for Embedded MemoriesDubey, Prashant; Garg, Akhil; Bhaskarani, Sravan Kumar · 2007
[IEEE 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems - Krakow, Poland (2007.04.11-2007.04.13)] 2007 IEEE Design and Diagnostics of Electronic Circuits and Systems - Built in Defect Prognosis for Embedded MemoriesDubey, Prashant; Garg, Akhil; Bhaskarani, Sravan Kumar · 2007
[IEEE IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) - Porto Alegre, Brazil (2007.03.9-2007.03.11)] IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07) - Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase PrognosisDubey, Prashant; Garg, Akhil; Bhaskarani, Sravan Kumar · 2007
[IEEE 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Arlington, VA, USA (2006.10.4-2006.10.4)] 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems - Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip CostGarg, Akhil; Dubey, Prashant · 2006