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[IEEE Comput. Soc. Press European Design and Test Conference. ED & TC 97 - Paris, France (17-20 March 1997)] Proceedings European Design and Test Conference. ED & TC 97 - Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks

[IEEE Comput. Soc. Press European Design and Test Conference. ED & TC 97 - Paris, France (17-20 March 1997)] Proceedings European Design and Test Conference. ED & TC 97 - Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks

Benini, L.; De Micheli, G.; Macii, E.; Poncino, M.; Scarsi, R.

作者Benini, L.; De Micheli, G.; Macii, E.; Poncino, M.; Scarsi, R.
文件大小794.93KB
发表时间1997
DOI10.1109/EDTC.1997.582409
页码514-520

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