Generating synthetic benchmark circuits for evaluating CAD tools
- 作者Stroobandt, D.; Verplaetse, P.; van Campenhout, J.
- 卷第19卷
- 期第9期
- 文件大小221.46KB
- 发表时间2000
- DOI10.1109/43.863641
- 页码1011-1022
Symbolic synthesis of clock-gating logic for power optimization of synchronous controllersBenini, L.; De Micheli, G.; Macii, E.; Poncino, M.; Scarsi, R. · ACM Transactions on Design Automation of Electronic Systems · 1999
[ACM Press the conference - Munich, Germany (1999..-..)] Proceedings of the conference on Design, automation and test in Europe - DATE '99 - Glitch power minimization by gate freezingBenini, L.; De Micheli, G.; Macii, A.; Macii, E.; Poncino, M.; Scarsi, R. · 1999
[IEEE Comput. Soc Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings - Munich, Germany (9-12 March 1999)] Design, Automation and Test in Europe Conference and Exhibition, 1999. Proceedings (Cat. No. PR00078) - Glitch power minimization by gate freezingBenini, L.; De Micheli, G.; Macii, A.; Macii, E.; Poncino, M.; Scarsi, R. · 1999
[IEEE Comput. Soc. Press European Design and Test Conference. ED & TC 97 - Paris, France (17-20 March 1997)] Proceedings European Design and Test Conference. ED & TC 97 - Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networksBenini, L.; De Micheli, G.; Macii, E.; Poncino, M.; Scarsi, R. · 1997