![[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designs]()
[IEEE 2011 IEEE 9th International Conference on ASIC (ASICON 2011) - Xiamen, China (2011.10.25-2011.10.28)] 2011 9th IEEE International Conference on ASIC - ADDLL/VDD-biasing co-design for process characterization, performance calibration, and clock synchronization in variation-tolerant designsWang, Jinn-Shyan; Yung-Chen Chien, ; Jia-Hong Lin, ; Cheng, Chun-Yuan; Ying-Ting Ma, ; Chung-Hsun Huang, · 2011