Cut-hole layout decomposition and synthesis to reduce the effect of edge-placement errorsLiu, Hongyi; Han, Ting; Chen, Yijian · Microelectronic Engineering · 2016

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 22 February 2015)] Design-Process-Technology Co-optimization for Manufacturability IX - Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimizationSturtevant, John L.; Capodieci, Luigi; Zhou, Jun; Liu, Hongyi; Han, Ting; Chen, Yijian · 2015

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 21 February 2016)] Design-Process-Technology Co-optimization for Manufacturability X - Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETsCapodieci, Luigi; Cain, Jason P.; Liu, Hongyi; Hong, Chuyang; Han, Ting; Zhou, Jun; Chen, Yijian · 2016

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 21 February 2016)] Alternative Lithographic Technologies VIII - A paradigm shift in patterning foundation from frequency multiplication to edge-placement accuracy: a novel processing solution by selective etching and alternating-material self-aligned multiple patterningBencher, Christopher; Cheng, Joy Y.; Han, Ting; Liu, Hongyi; Chen, Yijian · 2016

SPIE Proceedings [SPIE SPIE Advanced Lithography - San Jose, California, United States (Sunday 21 February 2016)] Design-Process-Technology Co-optimization for Manufacturability X - Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processesCapodieci, Luigi; Cain, Jason P.; Liu, Hongyi; Han, Ting; Zhou, Jun; Chen, Yijian · 2016