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[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Operation serializability for embedded systemsGupta, R.K. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - An automated design environment for micromechanical sensorsMurthi, A.; Rocaries, F. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Deterministic test pattern reproduction by a counterKagaris, D.; Tragoudas, S.; Majumdar, A. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Realistic fault extraction for boardsSousa, J.T.; Shen, T.; Cheung, P.Y.K. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Constructive analysis of cyclic circuitsShiple, T.R.; Berry, G.; Touati, H. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Surprises in sequential redundancy identificationIyer, M.A.; Long, D.E.; Abramovici, M. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Economics modelling and optimisation of MCM test strategiesDislis, C.; Jalowiecki, I.P. · 1996
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - High rate soft output Viterbi decoderLuthi, E.; Casseau, E. · 1996
Fault-secure parity prediction arithmetic operatorsNicolaidis, M.; Duarte, R.O.; Manich, S.; Figueras, J. · IEEE Design & Test of Computers · 1997
Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory ResourcesManich, S.; Garcia-Deiros, L.; Figueras, J. · 2007
[IEEE 2002 International Test Conference - Baltimore, MD, USA (7-10 Oct. 2002)] Proceedings. International Test Conference - RTL level preparation of high-quality/low-energy/low-power BISTSantos, M.B.; Teixeira, I.C.; Teixeira, J.P.; Manich, S.; Rodriguez, R.; Figueras, J. · 2002
[IEEE 22nd IEEE VLSI Test Symposium, 2004. - Napa Valley, CA, USA (25-29 April 2004)] 22nd IEEE VLSI Test Symposium, 2004. Proceedings. - BIST technique by equally spaced test vector sequencesManich, S.; Garcia, L.; Balado, L.; Lupon, E.; Rius, J.; Rodriguez, R.; Figueras, J. · 2004
[IEEE Comput. Soc. Press European Design and Test Conference - Paris, France (11-14 March 1996)] Proceedings ED&TC European Design and Test Conference - Achieving fault secureness in parity prediction arithmetic operators: general conditions and implementationsNicolaidis, M.; Manich, S.; Figueras, J. · 1996
[IEEE Comput. Soc 8th IEEE European Test Workshop (ETW 03) - Maastricht, Netherlands (25-28 May 2003)] The Eighth IEEE European Test Workshop, 2003. Proceedings. - On the selection of efficient arithmetic additive test pattern generators [logic test]Manich, S.; Garcia, L.; Balado, L.; Lupon, E.; Rius, J.; Rodriguez, R.; Figueras, J. · 2003
[IEEE Comput. Soc. Press 14th VLSI Test Symposium - Princeton, NJ, USA (28 April-1 May 1996)] Proceedings of 14th VLSI Test Symposium - Enhancing realistic fault secureness in parity prediction array arithmetic operators by I/sub DDQ/ monitoringManich, S.; Nicolaidis, M.; Figueras, J. · 1996