Editorial
- 期刊名称Virtual and Physical Prototyping
- 作者Rennie, Allan; Aitchison, David; Jacobson, David
- 卷第5卷
- 期第4期
- 印刷ISSN1745-2759
- 文件大小32.81KB
- 发表时间2010-12
- DOI10.1080/17452759.2010.530822
- 页码181-181
A Test Time Theorem and its ApplicationsVenkataramani, Praveen; Sindia, Suraj; Agrawal, Vishwani D. · Journal of Electronic Testing · 2014
Neural Network Guided Spatial Fault Resilience in Array ProcessorsSuraj Sindia, Vishwani D. Agrawal · 2013
Defect Level and Fault Coverage in Coefficient Based Analog Circuit TestingSuraj Sindia, Vishwani D. Agrawal, Virendra Singh · 2012
Defect Level Constrained Optimization of Analog and Radio Frequency Specification TestsSindia, Suraj; Agrawal, Vishwani D. · Journal of Electronic Testing · 2015
Parametric Fault Testing of Non-Linear Analog Circuits Based on Polynomial and V-Transform CoefficientsSuraj Sindia, Vishwani D. Agrawal, Virendra Singh · 2012
[IEEE 2009 Asian Test Symposium - Taichung, Taiwan (2009.11.23-2009.11.26)] 2009 Asian Test Symposium - Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial CoefficientsSindia, Suraj; Singh, Virendra; Agrawal, Vishwani D. · 2009
[IEEE 2014 15th Latin American Test Workshop - LATW - Fortaleza, Brazil (2014.3.12-2014.3.15)] 2014 15th Latin American Test Workshop - LATW - Specification test minimization for given defect levelSindia, Suraj; Agrawal, Vishwani D. · 2014